Scan coverage estimate

Have you ever been trying to figure out why you don’t get the desired 100% coverage when you are synthesizing your design, just to find yourself waiting for the project synthesis script to finish.

I have many times. So I have written a minimal script that does nothing, but reporting the scan coverage estimate. Since it does nothing but the thing you want, it is very very fast.

Make a file scan_estimate.tcl

#Read your HDL files
read_file -format vhdl{ /path/to/design-e.vhd \
            /path/to/design-a.vhd}

# Sadly you need a technology, the default tech does not have test models
set search_path     { /path/to/your/tech/lib }; #most likely, last dirname is synopsys
set target_library   { some_vendor_name_and_techname.db };

create_clock clk -period 5.0; #We dont care about freq, but need a clock
compile -exact_map -scan
create_port -direction in scan_en; #We need a scan enable port
set_dft_signal -view existing_dft -type Reset -port rstn -active_state 0
set_dft_signal -view existing_dft -type ScanClock -timing [list 40 60] -port clk
set_dft_signal -view existing_dft -type ScanEnable -active_state 1 -port scan_en
set_scan_configuration
create_test_protocol
insert_dft

#report the scan coverage estimate
dft_drc -coverage_estimate

Start your DesignCompiler in a shell

dc_shell -gui

In your dc-shell type

source scan_estimate.tcl

Many times the project synthesis script takes hours and hours. But reporting just a small design typically takes a minute or less. Thus cutting down turnaround times, and freeing up the very expensive DesignCompiler license for actual work.