Registers in an ASIC are described in many different places, for example in:

• Actual physical registers
• Block level test benches
• Top level test benches
• Block level models
• System architectural model
• Software
• Software help files
• Block documentation
• Chip documentation
• Chip datasheet

The register descriptions in the datasheet many times covers many hundreds of pages. Imagine if the registers are described independently in these +10 places: how many incompatible descriptions of the same thing will there be?

Clearly there is a need to describe the registers once, and generate all the other descriptions or views from the same source. Luckily the the fellows at http://www.accellera.org/activities/committees/ip-xact/ has set an industry standard to describe registers.

I had a little time over and took the opportunity to write a few registers description generators:

https://github.com/oddball/ipxact2systemverilog

The package contain these generators

ipxact2systemverilog
ipxaxct2vhdl
ipxact2rst

Through the reStructuredText (rst) file there are implicitly 2 other generators

ipxact2pdf
ipxact2html

Through .rst files it is also possible to generate .odt or .doc files, but writing documentation in those formats is an engineering sin.

In order to generate UVM or OVM packages, there are other generators available.
One nice tutorial can be found here

http://www.doulos.com/knowhow/sysverilog/ovm/tutorial_rgm_1/